Method for the comparison of electrical circuits

ABSTRACT

Various phases of the circuit design are specified in different notations, whereby each notation is based on the same circuit. Since the notations arise successively during the circuit design, whereby the circuit design covers a considerable time span, it should also be assured that a first change in a notation of an early phase corresponds to a second change in a notation of a later phase. For that purpose, the circuits underlying the notations are formally compared. Each notation describes the circuit as a boolean finite automaton, whereby a comparison of two automatons is implemented in that their input variables, output variables and operands are compared to one another. An allocation of operands corresponding to one another is determined on the basis of a status dependency graph, whereby a resolution with operands of the automatons is refined such that, preferably, corresponding allocations of operands of the automatons result. A coarsening method assures that no resolutions arise that make an allocation impossible.

BACKGROUND OF THE INVENTION

This application is based on and hereby claims priority to German PatentApplication No. 198 14 109.2 filed on Mar. 30, 1998, the contents ofwhich are hereby incorporated by reference.

The invention is directed to a method for comparing electrical circuitsto one another.

In the design of a digital circuit, the quality assurance before thestart of production requires 30% to 70% of the entire development time.During the quality assurance, attempts to find faults in the circuit aremade by intensive simulation. Even after the end of the simulation, onlya part of the behavior of a digital circuit has been investigated, sothat it must always be considered that faulty designs can go intoproduction. An inconsistency in an electrical circuit noticed after thebeginning of production and a correction following thereupon requiretime-consuming and expensive refitting work.

The quality assurance is intended to assure that description forms ofdifferent phase of the circuit design for a circuit exhibit identicalinput/output behavior. It is thereby customary to represent (digital)circuits as finite automatons with Boolean input/output and truthvalues. Prof. Dr. Hans-Jochen Schneider (Editor), “Lexikon derInformatik und Datenverarbeitung”, R. Oldenbourg Verlag Munich, 1986,ISBN 3-486-22662-2, pp. 51-54. When description forms of differentphases of the circuit design are compared to one another, then thecircuits underlying the description forms are thereby compared.

In the framework of generating models, circuits that derive from therespective design steps are imaged onto finite automatons. Adetermination regarding the extent to which inputs and outputs of theautomatons are to be allocated to one another follows (input/outputmatching). Whether identical input values also lead to identical outputsin the automatons is examined in view of this allocation. When this isnot the case, a diagnosis is produced that allows the user to analyzethe fault.

T. Filkorn, Symbolische Methoden für die Verifikation endlicherZustandssysteme, Dissertation, Institut für Informatik at the TechnicalUniversity, Munich, 1992, pp. 82-97. discloses a method with the objectof simplifying a product machine, i.e. a combination of two automatons.The set of all status transition functions is thereby investigated andresolved into sub-sets of functions that behave identically on the setof obtainable statusses. Given automatons similar to one another, thesesub-sets contain an equal number of functions from both automatons andare even often two-element, so that the allocation of the operandsproceeds therefrom. One disadvantage of this method is comprised thereinthat differences between the two automatons do not lead to a usableresult. When two status transition functions that logically belongtogether differ, then a correct allocation does not occur.

What is understood by status coding is a representation of a circuit inthe form of an automaton, whereby this automaton comprises statusses andstatus transition functions.

A structural comparison of two circuits is a matter of a comparison ofthe combinatorial logic representing the circuit, given the assumptionthat the status codings of both circuits have occured in the same way.

In a sequential comparison, identical input/output behavior of twocircuits is verified, whereby the respective circuits can exhibitdifferent status.

Structurally identical automatons exhibit the same status; structurallysimilar automatons exhibit nearly identical status.

What is understood below by a resolution is a set that is composed ofdisjunctive sets. A group is an element of a resolution, whereby thiselement again represents a set. A sub-resolution is a sub-set of aresolution. A refinement (of a resolution) derives from the wording as a“finer” subdivision of the resolution. The relationship that has beenpresented is explained on the basis of a brief example:

Basic set: {a, b, c, d, e} Resolution: {{a, b}, {c, d}, {e}} Group: {a,b] or {c, d} or {e} Sub-resolution: for example, {{a, b}, {e}} or   {{a,b}} or    {{c,d}, {e}} Refinement: {{a}, {b}, {c, d}, {e}}

SUMMARY OF THE INVENTION

An of the invention is to create a method for comparing electricalcircuits, to thus not have to completely cover the design process, and,given different but structurally automatons, to assure an efficientcomparison on the basis of an abstraction of status transition functionsof the automatons, which describe the electrical circuits.

The circuits to be compared can proceed from different description formsfor the design of an electrical circuit. It is to be assured that theelectrical circuits corresponding to the different description forms areidentical. Each description form represents a separate electricalcircuit.

According to the method of the invention for comparison of electricalcircuits, a representation of a first circuit is provided by a firstautomaton. A representation of a second circuit is provided by a secondautomaton. An allocation of input variables of the first automaton ontoinput variables of the second automaton and an allocation of outputvariables of the first automaton onto output variables of the secondautomaton is provided. A base set is provided with operands of the firstand of the second automaton. Preceding from a predetermined resolutionof the base set, implementing the following steps:

1) determining which data dependency exists between operands, inputvariables and output variables for each operand of the resolution,wherein

determining those operands and those input variables on which a statustransition function of the operand is dependent, and

determining those operands and those output variables that are dependenton the operand for each operand;

2) combining those operands that are determined by identical datadependencies according to step 1) in a group of the resolution; and

3) implementing step 2) for all operands, so that a refinement of theresolution is determined.

Operands of the respective group are considered allocated to oneanother. A comparison of the two circuits underlying the automatons isimplemented on the basis of the identified allocations.

A method for the comparison of electrical circuits is created wherein afirst circuit is represented by a first automaton and a second circuitis represented by a second automaton. Input variables and outputvariables of the first automaton are imaged onto corresponding inputvariables and output variables of the second automaton. A basic setcomprises operands of the first and of the second automaton. Proceedingfrom a resolution of the basic set, the following steps are implemented:

(1) For each operand of the resolution, a determination is made as towhich dependencies exist between operands, input variables and outputvariables, whereby operands from a group can be distinguished from oneanother;

(2) those operands that are defined by identical data dependenciesaccording to step (1) are combined in a group of the resolution and;

(3) step (2) is implemented for all operands, so that a refinement ofthe resolution is determined.

Operands of a group of the refinement are allocated to one another and acomparison of the electrical circuits underlying the automatons isimplemented on the basis of the identified allocation.

One step for the comparison of two circuits that are respectivelyrepresented by a finite automaton to one another is comprised in thepaired allocation of a respective operand of both automatons to oneanother, as a result whereof what status transition functions are to becompared and what operands are to be identified in the comparison(structural comparison) are determined.

A sequential comparison requires a predetermined variable ordering, i.e.a sequence, in which operands are noted and processed, whereby thissequence substantially determines the expense of the sequentialcomparison. When the variable ordering is determined with the inventivemethod, then a drastic reduction of the run time of the sequentialcomparison or a clearly reduced demand for memory capacity to be madeavailable results.

In a development of the invention, an iteration of the method isimplemented such that the refinement of the resolution is inserted as anew resolution and one continues with step (1) until no farther-reachingrefinement of the resolution is determined by a next iteration.

Advantageously, an identical number of operands of the first and of thesecond automaton are present in a group. The group is called balanced inthis case. A matching group is a two-element balanced group. When aplurality of matching groups are obtained at the end of the preferablyiterative application of the method, then an unambiguous allocation ofthe operands contained in the respective matching group resultstherefrom.

In another development, a refinement of the resolution is achieved withat least one of the following possibilities:

a) In a support method, those operands and those input variables onwhich the status transition function of the operand x depends aredetermined for each operand x;

b) in an inverse support method, those operands and those outputvariables that are dependent on the operand are determined for eachoperand.

Let it be thereby noted that the basic set preferably covers alloperands of both automatons. The dependency on the other operands of anautomaton is determined for each operand x for the respective automaton.A possible presentation occurs on the basis of a data dependency graph.The data dependency graph comprises a node for each operand of therespective automaton and an arrow from a node u to a node v when node ulies in the support of node v. Conversely, then node v then lies in theinverse support of the node u.

Another development of the invention is that refinements areadditionally generated on the basis of a simulation method in that, onthe basis of value occupancies of the input variables and of theoperands that are preferably randomly generated, identical valueoccupancies of the status transition functions underlying the operandsare determined.

Another development of the invention is comprised in correcting anincorrectly determined refinement of the resolution on the basis of acoarsening method, in that groups with a respectively different numberof operands of the first automaton and of the second automaton arecombined in a group.

In general, unbalanced groups of the resolution wherein an allocation ofoperands of the two automatons to be compared cannot occur arecounteracted by the coarsening method.

In the framework of an additional development of the invention, the twoautomatons are sequentially compared to one another. Precisely givensuch a sequential comparison, it is advantageous when the automatons tobe compared are structurally similar. A sequential comparison occurs inthat the first and the second automaton are operated with one another toform a product automaton. An input signal is applied both to the firstas well as to the second automaton, and the resulting output signals ofthe first and of the second automaton are compared to one another.Preferably, such a comparison is implemented with an exclusive-ORoperation that indicates with a output value “0” (or, respectively,“FALSE”) that the output signals of the two automatons are different.

Binary decision diagrams (BDDs) are preferably utilized in thesequential comparison (also see R. Bryant, Graph-based Algorithms forBoolean Function Manipulation, IEEE Trans. on Computers, Vol.C-35, No.8, August 1996, pp. 677-691.). A variable ordering within the BDDsdetermines the sequence in which the variables are proposed. How muchmemory the BDDs use and the time in which they can be processed areprescribed to a substantial extent by the variable ordering.

The method of the invention can be utilized for determining the variableordering. Thus, the variable ordering is determined according to theidentified allocations of the operands in that operands allocated to oneanother are arranged behind one another.

Exemplary embodiments of the invention are presented in greater detailon the basis of the following Figures.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a block diagram that shows various stages of the circuitdesign;

FIG. 2 illustrates a block diagram with method steps for comparing twocircuits;

FIG. 3, shows a first sketch with two status dependency graphs;

FIG. 4 illustrates a second sketch with two status dependency graphs;

FIG. 5 illustrates a sketch that shows a product automaton thatcomprises a first and a second automaton.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a block diagram that shows various stages (also: phases) ofthe circuit design.

A circuit can be described in various ways. In a step 101, a circuit isdescribed on register transfer level (RTL). A first network list 102 isproduced in a first synthesis step 104; and a second network list 108 isproduced in a second synthesis step 105. Such network lists arepresented in different notation. A final network list 103 is producedfrom the first network list 102 in a plurality of steps 104, 105 and109. The circuit is placed in production with the final network list103.

The steps 104, 105 and 109 preferably comprise an optimization of thelogic, whereby the number of flip-flops after the optimization is equalto the number of flip-flops before the optimization. Further, what isreferred to as a “scan path” is preferably inserted into the circuit,this enabling a testing of the component (chip) that is produced later.A basic clock is usually also correspondingly divided, so that this isavailable with good quality at various locations in the component(“clock tree”).

A circuit undergoes a number of phases during the design process,whereby several months pass before a corresponding, final network list103 has arisen from the RTL description. When changes in the RTLdescription are made during the design process, for example due tosuddenly occurring faults, then this usually has significant influenceon the network lists 102, 108 and, accordingly, on the final networklist 103 as well. Preventing, in particular, a renewed run-through ofthe entire development process and, thus, minimizing the enormous timeexpenditure is possible on the basis of the present invention.

Both the RTL description 101, the network lists 102 and 108 as well asthe final network list 103 represent independent descriptions of asingle circuit. In order to assure that the same circuit is reallypresented by the individual descriptions, the descriptions are comparedto one another. What is referred to as a synthesis comparison 106 ismade between the RTL description 101 and the network lists 102, 108, andwhat is referred to as a network list comparison 107 is made between thenetwork lists 102 and 108 or 102 and 103. The circuits on which therespective descriptions are based are compared to one another anddifferences are discovered on the basis of the formal verification.

Fundamentally, every individual process step can be compared to anotherprocess step, i.e. each description form can be compared to every otherdescription form.

Each description is based on a boolean automaton that comprises inputand output variables. When two of the automatons are compared to oneanother, then the input variables of the first automaton are to beimaged onto input variables of the second automaton and,correspondingly, to image the output variables of the first automatononto output variables of the second automaton. Further, numerousoperands, whose behavior is described with status transition functions,exist in the automatons. Another goal of the invention is to allocateoperands of the first automaton to operands of the second automaton,whereby every individual operand of the first automaton should beallocated to an operand of the second automaton, insofar as possible. Apaired comparison of operands enables a verification of the twoautomatons.

In view of their behavior in the different descriptions 101, 102, 108 or103, the finite boolean automatons do not exhibit any great differencessince, of course, the same circuit is described (in the ideal case). Inparticular, the invention employs status dependency graphs in order todraw conclusions about the significance of the operands and produce anallocation of the operands between the automatons. Such statusdependencies are shown by way of example in FIGS. 3 and 4.

Notations and names are introduced that are of significance below forthe explanation of the invention:

For two sets A and B,

A+B denotes the union,

A*B denotes the section (meet),

A−B denotes the set difference, and

{ } denotes the empty set.

A set of disjunctive, non-empty sets whose union yields M is called aresolution Z of a set M. An element from Z is called a group from Zbelow. The refinement Z′ of a resolution Z of the set M is a resolutionof M with the property that each element of Z′ is a sub-set (possiblyuntrue) of a group from Z.

Let a factorization A/U of a sub-set A of N with respect to a sub-set Uof the resolution Z of M be the set of groups from U that contain theelements of A.

Example

Z={{1, 2}, {3, 4,45}, {6, 7, 8}};

U={{1, 2}, {3, 4, 5}}

and

A={1, 6, 7}.

The following thus derives:

A/U={{1, 2}}.

If M be a set of variables and B be the set of boolean values {true,false}, then let B**M reference the set of all possible occupations ofthe variables with boolean values.

A boolean finite automaton is characterized by

the set I of its input variables (also: start variables),

the set S of its operands,

the boolean status transition function belonging to the set S thatimages the set B**(S*I) to B**S,

the set O of its output variables (also: end variables),

the boolean output function belonging to the set O that images B**S(S+I)to B**O, and

INIT, a set of initial statusses that is a sub-set of B**S.

It is assumed below that the operands, input variables and outputvariables of the two automatons have different names. From now on, let Sbe the set of operands of both automatons. A set of variables is calledbalanced when it contains the number of variables from each of theautomatons. A matching group is a two-element balanced set.

A successive refinement of the set S of all statusses of both automatonsis achieved with the invention. The individual resolutions shouldthereby be of such a nature that potentially allocated operands alwayslie in the same group. An unambiguous allocation is defined by matchinggroups.

First, input and output variables of the two automatons are allocated toone another. The input variables and output variables in an automatonare replaced by the respectively allocated input variables and outputvariables of the other automaton.

The method begins with a suitable initial resolution Z₀ of S. Thetrivial resolution {S} is preferably employed therefor.

The method defines a sequence Z₀, Z₁, Z₂, . . . of resolutions. Z_(i+1),is thereby generally a refinement of Z_(i) that is calculated on thebasis of the methods described below.

The support method, the inverse support method and the simulation methodare refinement methods. Which refinement methods are applied in whichsequence is dependent on the respective, individual case. The method isended when the resolution Z_(i) is composed only of matching groups orwhen no true refinement is achieved bu a further refinement step.

In the support method, a determination is made for each operand xregarding the operands and input variables on which its statustransition function depends. This set is called Support D(x) of x. TheSupport D(x) is modified such that variables of a group can bedistinguished therein in that exactly one representative is defined foreach group in the resolution Z_(i) and the variables in the Support D(x)are replaced by their representatives. Two operands enter into the samegroup in the new resolution precisely when their modified support is thesame and they were contained in the same group of the resolution Z_(i).

The inverse support method is similar to the support method: instead ofthe support D(x) of an operand x, the inverse support R(x) of theoperand x is determined. This corresponds to the set of all operands andoutput variables whose functions are dependent on the operands x.

The simulation methods determines—preferably randomly—a plurality ofvalue occupations for all input variables and operands wherein elementsof a group always have the same value. For each operand, the results ofits status transition function are then calculated under these valueoccupations. Two operands enter into the same group in the newresolution precisely when these results are the same and they werealready in the same group previously.

What all refinement methods have in common is that they calculate acertain information for each operand and do not distinguish betweenelements of a group of Z_(i) in this calculation. Consequently, twooperands that belong together from two structurally equivalentautomatons are not pulled apart.

A detailed description of how the respectively next resolution Z_(i+1)is calculated from a resolution Z_(i) follows.

Support Method

When I is the set of all input variables and IM is the resolution of Ithat corresponds to the image of the input variables (=input matching),then Y=IM+Z_(i) is a resolution of I+S.

U references a sub-set from Y. Further, let G be a group from Z_(i) thatis not a matching group. The support D of its status transition functionis determined for each operand x. G is divided such that operands withthe same factorization D/U lie in the same sub-group and operands withdifferent factorization D/U lie in different sub-groups. This isimplemented for each group G from Z_(i) that is not a matching group.Z_(i+1) is composed of all sub-groups that derive in this way and of allmatching groups from Z_(i).

The exact selection of U is preferably left up to the user.Possibilities for the selection of U are the sub-set of the matchinggroups of Y, the sub-sets of the balanced groups of Y or the entire setY.

Inverse Support Method

O references the set of all output variables and OM references theresolution into matching groups that corresponds to the allocation ofthe output variables (output matching). Further, let X=OM+Z_(i) be aresolution of O+S. U is a sub-set from X. The above-described criteriaapply for the selection of O. G is a group from Z_(i) that is not amatching group. The set R of the operands and output variables in thesupport of which x occurs is determined for each operand x from G. G isdivided such that operands with the same factorization R/U lie in thesame sub-group and operands with different factorization R/U lie indifferent sub-groups. This is carried out for all G from Z_(i) that arenot matching groups. Z_(i+1) is composed of all sub-groups that therebyresult and of the matching groups from Z_(i).

Implementation by Representatives

In the implementation of the support method, the factorization D/U isnot presented by a set of sets but by a set of representatives. For thepurpose, a representative set V is defined for U, i.e. a set thatcontains exactly one element from each group from U. In order to obtainthe representative presentation of D/U, it suffices to investigate eachelement a from the support D. When there is a group in U that containsa, then a is replaced by the representative of this group; otherwise, itis deleted.

A pseudo code similar to the programming language PASCAL is employed forthe following formal description of the method. The following speechconstructs are thereby preferably applied:

:=variable allocation

for each x in M do loop instruction that processes all elements of theset M

exists v such that Cond(v) is true when there is a value for v withwhich Cond(v) is satisfied and occupies v with this value

choose any y from M occupies y with an arbitrary element from the set M

choose_subset function for the selection of the sub-set U from aresolution

choose_representant defines the representative of a group

is_matching_group(G) is true for a matching group G, otherwise false

{ } references the empty set

support(x) defines the support of the operand x.

Program 1: Z_new := {}; U := choose_subset(Y); {* select representantand compute relation between any element of a group and its representant*} V := {}; for each G in U do begin v := choose_representant(G); foreach y in G do V := V + {(v, y)}; end; {* examine all groups in Zi *}For each G in Zi begin if is_matching_group(G) then Z_new = Z_new + {G}else begin {* compute relation between element and factorized support *}SupportRelation = {}; for each x in G do begin D := Support(x); {*factorize support *} D_fak := {}; for each d in D do if exists v suchthat (v, d) in V then D_fak := D_fak + {v}; SupportRelation :=SupportRelation + {(x,D_fak)}; end; {* split G according to differentsupports *} repeat {* take some element *} choose any (x, D_fak) fromSupportRelation; G_new := {x}; SupportRelation := SupportRelation − {(x,D_fak)} while exists y such that (y, D_fak) in SupportRelation beginG_new := G_new + {y}; SupportRelation := SupportRelation {(y, D_fak)};end Z_new := Z_new + {G_new}; until SupportRelation = {}; end; end;

The inverse support method is implemented analogous thereto.

Alternative Implementation

The alternative implementation of the inverse support method presentedbelow avoids an explicit determination of the inverse support. Thesupport D(M) for each group M from U is defined as a union of thesupport of the elements of M. Each group G from Z_(i) that is not amatching group is split such that two elements x and y from G come tolie in the same sub-group when it applies for each M from U that x and yeither both lie in D(M) or neither of the two lies therein. Otherwise,they should be contained in different sub-groups. Z_(i+1) again containsall sub-groups that have arisen in this way and the matching groups fromZ_(i).

Program 2 shows a possible implementation of the method. The samenotation as described above applies, whereby

matching_groups(Z) references the set of matching groups of Z.

Program 2: ZG := Zi-matching_groups(Zi); for each M in U do begin ZGnew:= {}; D := Support(M); for each G in ZG do begin A := G-D; if (A = {}or A = G) then ZGnew := ZGnew + {G} else ZGnew := ZGnew + {A, G * D};end; ZG = ZGnew; end; Zi+1 = ZGnew + matching_groups(Zi);

This alternative implementation is based thereon that y lies in thesupport D(x) of an operand x precisely when the operand x lies in theinverse support R(y). For each M from U, x from D(M) is thus equivalentto M from R(x)/U. As a result of the alternative implementation, twooperands x and y remain in the same group of Z_(i+1) when they lie inthe same group of Z_(i) and when each D(M) contains either both orneither, i.e. when R(x)/U and R(y)/U both contain M or neither containsM. R(x)/U and R(y)/U are thus also equal because they must be sub-setsof U. Conversely, x and y are separated from a group of Z_(i) when thereis at least one M, so that one of the two operands lies in D(M) and theother does not. M is then contained in only one of the two factor setsR(x)/U and R(y)/U and R(x)/U or, respectively, R(y)/U are different. Thedivision Z_(i+1) is thus the same that is also obtained by theapplication of the inverse support method.

Analogous to this implementation, the support method can also beimplemented upon employment of the inverse support.

Simulation Method

Let, as declared above, Y=IM+Z_(i) apply as a resolution of I+S. x is anoperand and f_(x) is the corresponding status transition function. Let Pbe a set of value occupations of the operands and input variables thatis selected such that variables from the same group of Y are occupiedwith the same values. P will generally be only a small selection of allpossible value occupations. In particular, the set P can be arbitrarilydefined.

Each group from Z_(i) that is not a matching group is split intosub-groups, so that two elements x and y from G lie in the samesub-group precisely when their status transition functions f_(x) andf_(y) supply the same values for all value occupations from P. Z_(i+1)is again formed from the sub-groups deriving in this way and from thematching groups from Z_(i).

Program 3 shows an implementation of the simulation method. Thedesignations as above again apply, plus:

P references the set of simulation stimuli, i.e. nearly arbitrary testoccupations

f_(x)(v) references the application of the status transition function ofx to the value occupation v

generate_patterns(Y) defines the set P, whereby Y is handed over asparameter because the value occupations for all variables of a group ofY should be the same.

Program 3: ZGnew :={}; ZG := Zi - matching_groups(Zi); P :=generate_patterns(Zi + IM); for each v in P do begin ZGnew := {}; foreach G in ZG do begin choose any x from G A := {x}; B := {}; G := G −{x}; Ref := fx(v); for each y in G do begin if Ref = fy{v} then A := A +{y} else B := B + {y} end; if B = {} then ZGnew := ZGnew + {A} elseZGnew := ZGnew + {A, B}; ZG := ZGnew; end; end; Zi+1 := ZGnew +matching_groups(Zi);

Coarsening Method

The coarsening method corrects a faulty division that can derive whenthe automatons are in fact structurally similar but not identical.Fundamentally, unbalanced groups that have arisen in the precedingrefinement steps should thereby be re-combined. For that purpose, apreviously calculated resolution Z_(k), k≦i that serves as referenceresolution must be defined. For each group G from Z_(k), the coarseningmethod then determines the unbalanced sub-groups in Z_(i) that aresub-set of G. These unbalanced sub-groups are united to form a groupZ_(i+1). Moreover, Z_(i+1) should contain all balanced groups of Z_(i).It is desirable that additional balanced groups or even matching groupsarise as a result of the unification.

The reference resolution that is selected is left up to the individualcase.

However, a resolution should be selected that, on the one hand, containsoptimally small groups and of which it can be assumed, on the otherhand, that operands that belong together lie in the same group.Preferably, the result of the preceding coarsening method is defined asresolution Z_(k).

Result

In the ideal case, the last resolution Z that is calculated is composedonly of matching groups from which an allocation of the operandsdirectly proceeds.

Unbalanced groups or groups with more than two elements can also remain.The reason for this can, on the one hand, be that the methods areemployed for the dividing abstract from the actual status transitionfunctions and output functions. Information required for a more exactmatching are lost in this abstraction. On the other hand, redundanciescan be present in the circuit. When, for example, both automatons haverespectively two operands x, y and x′, y′ to be allocated to one anotherand having identical status transition functions and x, y or,respectively, x′, y′ either lie in common or not at all in the supportof the other variable, the method will terminate with a resolution inwhich there is a group that contains all four operands because thestatus transition functions supply no information for the division.

A third possible reason is comprised therein that the automatons are infact similar but nonetheless differ such that some statusses cannot beallocated.

It is not disturbing for a sequential comparison when the resultresolution contains Z groups that are not matching groups. Z is usuallyfine enough in order to define a new variable ordering for the largerautomaton that approximately coincides with the variable ordering of thesmaller automaton. The larger automaton also usually becomes smaller dueto the switch to this inexactly defined variable order.

In a structural comparison, the operands in the disturbing groups musteither be excluded from the comparison or the resolution must beinvestigated further. Such a farther-reaching investigation could becomprised therein that a user makes further inputs or an allocation ismade on the basis of the names of the operands.

FIG. 2 shows a block diagram that exhibits method steps for thecomparison of two circuits.

In a step 201, two circuits are respectively represented by finiteautomatons. Boolean automatons are preferably used for this purpose.

In a step 102, input variables of the first automaton are imaged intoinput variables of the second automaton (input matching) and outputvariables of the first automaton are imaged onto output variables of thesecond automaton (output matching) (allocation of the input and outputvariables). An initial resolution S₀ is prescribed in a step 203. Arefinement of the initial resolution is defined in a step 204. Aninquiry (see step 205) determines whether further refinements of theresolution can be defined. When this is not the case, then the operandsare allocated on the basis of the identified refinement according to thespecific groups of the resolution determined by the refinement (see step206), and the circuits are compared in a step 207 on the basis of theallocation that has been made. When it turns out in the inquiry in thestep 205 that further refinements can be defined, then the method isiteratively continued with step 204, i.e. the nest refinement isdefined.

Examples

Example for Support Method and Inverse Support Method

FIG. 3 shows two status dependency graphs 301 and 302 that areinvestigated for differences according to the method for comparing twocircuits.

The status dependency graph 301 has a node for each operand and an arrowfrom node u to node v when u lies in the support of v. Denoting beloware:

i1, i2 input variables of the first automaton

i1′, i2′ input variables of the second automaton

s1, s2, s3, s4 operands of the first automaton

s1′, s2′, s3′, s4′ operands of the second automaton

o1, o2 output variables of the first automaton, and

o1′, o2′ output variables of the second automaton.

Upon application of the support method, the following supports can beread from the status dependency graphs:

D ₁ ={i 1}, D ₂ ={i 1, i 2}, D ₃ ={s 1, s 2}, D ₄ ={s 1, s 2},

(analogous for the second automaton).

The resolution

Z ₀ ={{s 1, s 2, s 3, s 4, s 1′, s 2′, s 3′, s 4′}}

of the operands forms the basis, i.e.

Y ₀ ={{i 1, i 1′}, {i 2, i 2′}, (s 1, s 2, s 3, s 4, s 1′, s 2′, s 3′, s4′}}.

Let U₀=Y₀ apply and let {i1, i2, s1} be the representative set of U₀.

Given identification of the representatives with the groups theyrepresent, the following derives:

D ₁ /U ₀ =D _(1′) /U ₀ ={i 1},

D ₂ /U ₀ =D _(2′) /U ₀ ={i 1, i 2}

D ₃ /U ₀ =D _(3′) /U ₀ ={s 1},

D ₄/U₀ =D _(4′) /U ₀ ={s 1}.

The new resolution Z₁ derives as:

Z ₁ ={{s 1, s 1′}, {s 2, s 2′}, s 3, s 4, s 3′, s 4′}}.

By renewed application of the support method, with

Y ₁ ={{i 1, i 1′}, {i 2, i 2′}, {s 1, s 1′}, {s 2, s 2′}, {s 3, s 4, s3′, s 4′}}.

and with U₁=Y₁ and the representative set {i1, i2, s1, s2, s3}, thefollowing derives:

D ₁ /U ₁ =D _(1′) /U ₁ ={i 1},

D ₂ /U ₁ =D _(2′) /U ₁ ={i 1, i 2}

 D ₃ /U ₁ =D _(3′) /U ₁ ={s 1, s 2}

D 4/U 1 =D _(4′) /U ₁ ={s 1, s 2}

No additional refinement of Z₁ follows therefrom. The fact that thesecond application of the support method already yields no additionalrefinement is a special characteristic of the example.

Proceeding from Z₁, a farther-reaching refinement can be found on thebasis of the inverse support method. The following applies:

R ₁ ={s 3, s 4},

R ₂ ={s 3, s 4},

R ₃ ={o 1}

R ₄ ={o 2}.

For Z₁, the resolution of the operands and output variables is:

X ₁ ={{o 1, o 1′}, {o 2, o 2′}, {s 1, s 1′}, {s 2, s 2′}, {s 3, s 4, s3′, s 4′}}.

With the representative set V={o1, o2, s1, s2, s3}, the followingapplies:

R ₁ /X ₁ =R _(1′) /X ₁ ={s 3},

R ₂ /X ₁ =R _(2′) /X ₁ ={s 3},

R ₃ /X ₁ =R _(3′) /X ₁ ={o 1},

R ₄ /X ₁ =R _(4′) /X ₁ ={o 2},

so that Z₁ is refined to:

Z ₂ ={{s 1, s 1′}, {s 2, s 2′}, {s 3, s 3′}, s 4, s 4′}}.

The allocation is unambiguously defined; only matching groups are nowpresent.

Example of the Coarsening Method

FIG. 4 is considered below as an example of the coarsening method. FIG.4 shows the two status dependency graphs 401 and 402 that are notstructurally equivalent.

The first application of the support method proceeds as in the aboveexample for FIG. 3. Although D_(4′)={s2′} (and not {s1′, s2′} as above)applies, this difference being compensated by the factorization to U₀.Z₁ therefore derives as above. The following, however, applies when thesupport method is applied anew:

D ₁ /U ₁ =D _(1′) /U ₁ ={i 1},

 D ₂ /U ₁ =D _(2′) /U ₁ ={i 1, i 2}

D ₃ /U ₁ =D _(2′) /U ₁ ={s 1, s 2}

D 4/U ₁ ={s 1, s 2} but D _(4′) /Y ₁ ={s 2},

so that the group {s3, s3′, s4, s4′} for Z₂ would first be divided intothe sub-groups {s3, s3′, s4} and {s4′}. However, the coarsening method(with k=1) recombines these sub-groups. Having operands s4 and s4′ thatactually belong together being pulled aprt is thereby prevented. Anunambiguous allocation can again be undertaken after application of theinverse support method.

Implementation Example

In addition to the designations defined above, let the following alsoapply below:

Support_Methode(Z,X)

Inverse_Support_Methode(Z,X)

Simulations_Methode(Z)

Coarseningstep(Z,Z_Ref)

designate applications of the respective method (as presented in detailabove). In the support method and the inverse method, X indicates how Uis defined: Given

X=total all groups of the resolution should be taken

X=matching only the matching groups should be used.

The following designations are also employed in Program 4:

Z_Ref indicates which resolution is defined as reference resolutionZ_(k) in the coarsening step (coarsening method),

completely_matched(Z) is true when all groups from Z are either matchinggroups or comprise only operands of one automaton.

The indicated implementation in Program 4 is a large loop that breaksoff when either ‘completely_matched” is satisfied or when no furtherdivision (further resolution) is found by the large loop.

The application of the individual methods is repeated until a fixedpoint has been reached.

Program 4: Z = {S}, repeat Z_Reference1 = Z; repeat Z_Reference2 := Z;Z: = Inverse_Support_Methode(Z, matching); Z: = Vergröberungsschritt(Z,Z_Reference2); until Z = Z_Reference2; if completely_matched(Z) thenexit; repeat Z_Reference3 = Z; Z := Support_Methode(Z, total); until Z =Z_Reference3; Z := Vergröberungsschritt(Z, Z_Reference2); ifcompletely_matched(Z) then exit; repeat Z_Reference2: = Z; Z :=Inverse_Support_Methode(Z, matching); Z := Vergröberungsschritt(Z,Z_Reference2); until Z = Z_Reference2; if completely_matched(Z) thenexit; repeat Z_Reference3 = Z; Z: = Inverse_Support_Methode(Z, total);until Z = Z_Reference3; Z: = Vergröberungsschritt(Z, Z_Reference2); ifcompletely_matched(Z) then exit; repeat Z_Reference2 := Z; Z :=Inverse_Support_Methode(Z, matching); Z := Vergröberungsschritt(Z,Z_Reference2); until Z = Z_Reference2; if completely_matched(Z) thenexit; Z := Simulations_Methode(Z); Z := Vergröberungsschritt(Z,Z_Reference2); until Z = Z_Reference1;

FIG. 5 shows a product automaton that comprises a first automaton and asecond automaton.

In order to implement a sequential comparison of two automatons thatrespectively represent an underlying electrical circuit, the twoautomatons 1 and 2 (see FIG. 5, 504 and 505) are interleaved in thatinput variables are allocated to one another and resulting output values502 and 503 are compared to one another. The comparison preferably withan EXOR-operation that indicates an inequality of output values 502 and503 with a logical “1”.

A variable arrangement (see Bryant) that is offered by matching groupsof the method of the invention is required for the sequentialcomparison. Advantageously, functions of the finite automatons arepresented BDDs (see Bryant).

Although various minor changes and modifications might be proposed bythose skilled in the art, it will be understood that our wish is toinclude within the claims of the patent warranted hereon all suchchanges and modifications as reasonably come within our contribution tothe art.

The following publications are cited in the course of this document:

[1] Prof. Dr. Hans-Jochen Schneider (Editor), “Lexikon der Informatikund Datenverarbeitung”, R. Oldenbourg Verlag Munich, 1986, ISBN3-486-22662-2, pp. 51-54.

[2] T. Filkom, Symbolische Methoden für die Verifikation endlicherZustandssysteme, Dissertation, Institut für Informatik at the TechnicalUniversity, Munich, 1992, pp. 82-97.

[3] R. Bryant, Graph-based Algorithms for Boolean Function Manipulation,IEEE Trans. on Computers, Vol.C-35, No. 8, August 1996, pp. 677-691.

What is claimed is:
 1. A method for comparison of electrical circuits,comprising: providing a representation of a first circuit by a firstautomaton; providing a representation of a second circuit by a secondautomaton; providing an allocation of input variables of the firstautomaton onto input variables of the second automaton and an allocationof output variables of the first automaton onto output variables of thesecond automaton; providing a base set with operands of the first and ofthe second automaton, proceeding from a predetermined resolution of thebase set, implementing the following steps (1) determining which datadependencies exist between operands, input variables and outputvariables for each operand of the resolution, wherein determining thoseoperands and those input variables on which a status transition functionof the operand is dependent, and determining those operands and thoseoutput variables that are dependent on the operand for each operand, (2)combining those operands that are determined by identical datadependencies according to step (1) in a group of the resolution, and (3)implementing step (2) for all operands, so that a refinement of theresolution is determined, whereby operands of the respective group beingconsidered allocated to one another; and implementing a comparison ofthe two circuits underlying the automatons on the basis of theidentified allocations.
 2. The method according to claim 1, whereby aniteration is implemented such that the refinement of the resolution isutilized as a new resolution and one continues with step (1) until nofurther refinement is determined by a further iteration.
 3. The methodaccording to claim 1 wherein additionally, a plurality of operands arecombined in a group when identical value occupations of the outputvariables are identified for predetermined value occupations of theinput variables and the operands based on the status transitionfunctions underlying the operands.
 4. The method according to claim 1wherein a faulty refinement is corrected in that two groups having arespectively different number of operands of the first automaton and ofthe second automaton are combined in a group.
 5. The method according toclaim 1 wherein the first automaton and the second automaton areoperated to form a product automaton, whereby a variable ordering isdetermined in that operands that have been allocated to one another arearranged lying close to one another.
 6. The method according to claim 5wherein a sequential comparison of both circuits is implemented in thata sequence of the operands in binary decision diagrams is defined by thevariable ordering.
 7. A method for comparison of first and secondcircuits represented by first and second automata, respectively,comprising: obtaining a predetermined resolution of a base setcontaining operands of the first and second automata with allocation ofinput and output variables of the first automaton onto input and outputvariables of the second automaton, respectively; determining as datadependencies for each operand a first set of other operands and inputvariables on which a state transition function of the operand isdependent and a second set of other operands and output variables thatare dependent on the operand; forming groups of similar operands, wherethe similar operands in each group have identical data dependencies andare considered allocated to one another; and comparing the first andsecond circuits underlying the first and second automata based on theallocation and the groups of similar operands.
 8. A method for analysisof first and second circuits represented by first and second automata,respectively, comprising: obtaining a predetermined resolution of a baseset containing operands of the first and second automata; applying asupport method and an inverse support method to identify datadependencies between the operands, input variables and output variablesin the first and second automata; and forming groups of operands havingidentical data dependencies.